1. Field of the Invention
This invention relates to semiconductor memory devices and more particularly to CMOS devices with enhanced ESD performance.
2. Description of Related Art
Junction leakage and junction short circuits to the substrate are more and more likely to occur in advanced technology devices as the dimensions of the devices forming those circuits become smaller and smaller.
U.S. Pat. No. 5,514,611 of Kim et al. for "Method for Manufacturing a Semiconductor Memory Device Having a Read-Only Memory Cell" shows a S/D (source/drain) structure with three I/I (Ion Implanted) doped regions.
U.S. Pat. No. 5,559,352 of Hsue for "ESD Protection Improvement" shows an ESD circuit with three I/I doped regions.
U.S. Pat. No. 5,493,142 of Randazzo et al. for "Input/Output Transistors with Optimized ESD Protection" has a lightly doped region disposed near the gate and the surface of the substrate. A sidewall oxide layer is selectively etched to extend laterally from a gate by a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may extend laterally an appreciable amount in that direction. Heavily doped S/D regions are implanted in the substrate. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.
U.S. Pat. No. 5,130,760 of Matzen et al. for "Bidirectional Surge Suppressor Zener Diode Circuit With Guard Ring" describes a semiconductor device incorporating doped regions of a substrate and epitaxial layers which result in a dual Zener diode arrangement having the Zener diodes associated in an opposite polarity arrangement.